1. Technical Field
The present invention relates generally to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundancy without a performance penalty.
2. Description of Related Art
A potential consequence of using a redundant cell array to repair a high-speed semiconductor memory device having a defect in a memory array is a decrease in the speed of operation, which can result in poor performance and operation of the semiconductor memory device. Various techniques have been developed to address performance penalties associated with repairing semiconductor chips.
One method for preventing performance loss as a result of repairing a semiconductor memory is disclosed in U.S. Pat. No. 5,793,683 (hereinafter, the ""683 patent) entitled xe2x80x9cWordline and Bitline Redundancy With No Performance Penalty,xe2x80x9d issued on Aug. 11, 1998. FIG. 1 is a block diagram of a memory array with redundancy as disclosed in the ""683 patent and FIG. 2 is a diagram of a redundancy circuit as disclosed in the ""683 patent. Referring to FIG. 1, a separate default array 1 and redundant array 4 are provided. As explained in detail in the ""683 patent, at the start of a given (read or write) cycle, an applied address is sent to both the normal array 1 and the redundancy calculation module 3. While accessing the normal array 1, the redundancy calculation 3 determines if the applied address matches any defective addressed stored in the fuse banks, and if so, accesses the redundant array 1.
Data read out of the arrays 1 and 4 are supplied to a multiplexer 5, which is controlled by selection signal (xe2x80x9credundancy activexe2x80x9d) output from the redundancy calculation module 3. By way of example, during a read cycle, if the redundancy calculation module 3 determines that the applied address corresponds to defective memory cells, the access is implemented in the redundant array 4 irrespective of the operation in the default array 1. If the redundant array 4 is accessed during a read, then the multiplexer 5 will selected the output of the redundant array, thereby implementing a redundancy operation. Accordingly, during read and write accesses, the redundancy calculation and redundant array access is performed in parallel with the normal array access. Thus, the performance is not degraded by the redundancy, if the redundancy calculation and redundant array access is not greater that the delay through the normal array.
Referring to FIG. 2, a diagram illustrates the structure of the redundant array 4 of FIG. 1 in greater detail. A plurality of redundant wordline blocks of cells WLR0-WLR7 and a plurality of redundant bitline blocks of cells BLRO-BLR7 are mapped into the array 4 as blocks of cells. The redundant array 4 allows a row repair WL at an upper portion thereof and a column repair BL thereof. Wordline decoders 6 decode the word addresses and bitline decoders 8 decode the bit addresses. A selector 7, which is controlled by the redundancy calculation module 3, supplies these addresses. Thus, the bit line decoding in the redundant array 4 varies with whether the selector 7 selects the row repair or the column repair. A more detailed explanation of the structure and operation of the circuits of FIGS. 1 and 2 is provided in the ""683 patent.
The conventional redundancy techniques described above afford an advantage of reduction in the speed performance penalty. One disadvantage is that the cell array is increased in size toward the row direction, thus, resulting in an increase in the area of the chip. Indeed, based on the implementation, as the redundant cell array increases in the row direction, additional bit line decoders and sense amplifiers S/A are needed, and the write driver W/D array and data line bus must be increased, thus requiring additional chip space.
Accordingly, it is an object of the present invention to provide a semiconductor memory device having redundancy without performance penalty during a redundancy operation, while minimizing the size of the redundancy array to minimize the chip size, as well as minimize current consumption during a redundancy operation.
In one aspect of the present invention, a semiconductor memory device comprises:
a default array block comprising a default array and sense amplifier;
a row redundant array block, independent of the default array, comprising row redundant arrays for compensating for a deficiency in a row direction;
a column redundant array block, independent of the default array, comprising column redundant arrays for compensating for deficiency in a column direction;
a controller for generating a first control signal that is commonly applied to the default array, row redundant array block, and column redundant array block; and
a redundant calculation circuit, responsive to the first control signal and an address signal, for generating a second control signal to the row and column redundant array blocks and to determine whether a redundant array is accessed, and for generating a third control signal to disable the sense amplifier of the default array during a redundant array access.
In another aspect, the row redundant array block and the column redundant array block each comprise a sense amplifier, a word line driver, and a decoder.
In yet another aspect, the row redundant array block, the column redundant array block and the default array block share a common data line.
In another aspect of the invention, the semiconductor memory device further comprises a multiplexer, operatively connected to data lines of the row redundant array block, data lines of the column redundant array block and data lines of the default array block, to selectively output data from the row redundant array block, column redundant array block and the default array block.
In yet another aspect, the row redundant arrays are mapped so that column addresses of the default array become row addresses, and the column redundant arrays are mapped so that a portion of the row addresses of the default array become column addresses.
In another aspect of the present invention, a method is provided for managing a memory array in a semiconductor memory device, wherein the memory array comprises a default array and a redundant array of memory cells, wherein the method comprises the steps of:
mapping a row redundant array so that column addresses of the default array become row addresses;
accessing the row redundant array to compensate for a deficiency in a row direction of the default array;
mapping a column redundant array so that a portion of row addresses of the default array become column addresses;
accessing the column redundant array to compensate for a deficiency in a column direction of the default array; and
disabling operation of a sense amplifier of the default array during an access of one of the row redundant array and column redundant array.
These and other objects, features and advantages of the invention will become more apparent from the following detailed description of preferred embodiments made with reference to the accompanying drawings.